Graphitron: A Domain Specific Language for FPGA-Based Graph Processing Accelerator(…)
summary
Graphitron is a DSL that compiles graph code to HLS-based FPGA kernels (evaluated on a Xilinx U280), auto-infers processing paradigm and applies burst read/write, URAM caching and stream shuffling to match vertex- or edge-centric patterns. It switches transparently between hybrid VCP/ECP based on frontier size, runs five algorithms on six datasets (BFS, SSSP, PageRank, PPR, GAT) and reports comparable or better throughput than a state-of-the-art FPGA framework (wins on BFS/SSP, slightly slower on PageRank) and 71–240× over naive HLS.
AI-written summary · about
chapters (15)
- 0:00Introduction
- 0:45FPGA graph processing motivation
- 3:12FPGA graph framework limits
- 5:38Graphitron DSL goals
- 6:44Graphitron workflow
- 8:32DSL design and model
- 10:19Compiler front-end and IR
- 11:02Compiler middle-end optimizations
- 12:31Memory access optimizations
- 13:34Generated accelerator
- 15:00Evaluation and benchmarks
- 16:52Performance results
- 17:57Design benefits
- 18:39Conclusion and future
- 19:00Q&A
related talks
43mSoftware Development Trends for FPGAs
40mFPGA Design with Chisel
17mAccelerating Designs for SoC FPGA Using Simplified High-Level Synthesis Flows
14m(WIP) A Flexible-Granularity Task Graph Representation and its Generation from C(…)
01h 03mOLD VERSION: Building Abstractions at the Hardware-software Boundary
20mOpen-Source FPGAs: Tools, Flows, and Visualization
01h 10mHardware DSLs
21mA Functional Approach to Synthesizing Routable Programmable Accelerators for Neural(…)