AMD-vIOMMU: A Hardware-assisted Virtual IOMMU Technology
summary
Describes a hardware-assisted AMD vIOMMU that replaces slow shadow host tables with nested IO page tables so guests use v2 I/O page tables (IOVA→GPA) while the host maps GPA→SPA, moves per-VM command/event/PPR buffers and guest MMIO into a private IOMMU address space accessed by new VF/VF-control MMIO bars, offloads emulation, and needs qemu and kernel changes (new device model, new ioctl interface, guest DMA driver v2 support). Design supports hybrid emulated and passthrough devices and claims scale to up to 64k VMs.
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chapters (14)
- 0:00Introducción
- 0:23Agenda
- 1:22AMD IOMMU DMA-Remap
- 5:33DMA-Remap Support for SW-IOMMU
- 8:29Nested Page-table Support for HW-VIOMMU
- 9:28Hybrid System Model: SW+HW VIOMMU
- 10:46HW Changes : IOMMU Private Address Space
- 12:06HW Changes : IOMMU VF and VF Control MIMIO BARS
- 13:07HW Changes : New IOMMU Commands and Events
- 14:57Host IOMMU Driver Changes
- 16:41QEMU Changes : New HW VIOMMU Device Model
- 18:22QEMU / Host AMD IOMMU Driver Changes : New Dev FS and IOCTL
- 19:00Guest AMD IOMMU Driver Changes
- 20:17Summary & Discussion
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