Powered by Less: Low Power Circuit Synthesis
summary
An automated RTL-to-RTL framework named Rover uses e-graph rewriting to combine arithmetic rewrites with clock/data gating and transparent-register insertion, simulates switching activity by sampling one node per e-class, and extracts designs with a power-aware cost model; the flow reports up to 33.9% total power reduction on benchmarks. It encodes optimizations as local rewrites, handles data gating and clock gating via register fusion, and currently struggles to express global resource sharing across distant nodes.
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chapters (13)
- 0:00Low power circuit synthesis
- 1:27Motivation for power optimization
- 3:12Behavioral synthesis for power
- 4:56Switching activity reduction
- 8:08Exploiting redundancy
- 10:58Data gating and registers
- 13:23Clock gating as rewriting
- 14:47Arithmetic and power optimizations
- 15:52EGAP power evaluation
- 17:39Case study and results
- 19:23Resource sharing challenges
- 20:05Future work and internships
- 21:08Q&A
