Reimagining SerDes for Scalable AI
summary
Claim: model sizes doubling every 3–4 months forces interconnects from 112→224→448 Gbps and PCIe from 64→128→258 Gbps, creating bandwidth and power shortfalls. Implementation details: PAM4 DSP with multi‑tap FFE/DFE plus CTLE and high‑performance ADC/DACs, ML for calibration and adaptation, advanced CDR and LDPC/RS FEC. Measured targets: long‑reach channels 35–50 dB loss, link power ~4–5 pJ/bit today, co‑packaged optics and chiplet packaging claim 5–8× bandwidth and 2–3× power reduction.
AI-written summary · about
chapters (11)
- 0:00Introduction to Scalable AI Architectures
- 0:29Agenda Overview
- 0:40AI Workload Impact on Interconnect Designs
- 2:17Challenges in Signal Integrity
- 5:18Innovations in SERDES Design
- 6:22Machine Learning and Advanced Techniques in SERDES
- 7:39Architectural Tradeoffs and Configurability
- 9:17Power Efficiency Strategies
- 10:12Holistic Solution Strategies
- 12:24Future Directions in SERDES for AI
- 13:56Key Takeaways and Conclusion
related talks
19mAI/ML Networking Challenges: The Fast and the Finicky!
18mCo-Designing Communication for AI Accelerators
22mWednesday Lightning Talks
22mCurrent State of AI
18mCo-Designing Communication for AI Accelerators
33mAI and SDR: Software Meets Hardware Again...
40mOptimize Your AI Cloud Infrastructure: A Hardware Perspective
28mThe AI Tipping Point