Pasquale Albert Magyar
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| title | conference | date |
|---|---|---|
| Rocket Engines: Low Effort Design Reuse In RISC V Implementations | 7th RISC-V Workshop 2017 | 2017-11-28 |
A new three‑stage core called Bottlerocket reuses RocketChip subcomponents to produce an RV32IMC microcontroller-style CPU with privilege 1.10, SiFive debug… | ||
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