PMEvo:portable inference of port mappings for out-of-order processors by evolutionary optimiz

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PMEvo infers processor port mappings from timed short microbenchmarks rather than platform-specific performance counters, using an evolutionary algorithm that optimizes candidates against an analytical throughput model solved by a custom bottleneck simulation algorithm. The prototype recovers Skylake mappings with accuracy competitive to counter-based tools, and produces usable mappings for AMD Zen+ and ARM Cortex-A72 where prior methods cannot apply. The tool predicts per-basic-block throughputs within practical error bounds and yields compact, interpretable port mappings.

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1. 0:00PMEvo and processor architecture
2. 2:49Hardware performance counters limits
3. 4:14Throughput-based port mapping
4. 7:43Modeling throughput and port mapping
5. 10:31Evolutionary algorithm for port mapping
6. 13:19Fitness goals and experiments
7. 16:28Implementation and evaluation
8. 19:00Comparison with state-of-the-art
9. 23:57Results and future work
10. 25:10Q&A: Port mapping in compilers