Lightweight Hypervisor Verification: Putting the Hardware Burger on a Diet

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" summary

Lightweight verification leverages Sail RISC V specs compiled to a Rust model and the Connie verifier to check per‑instruction faithful emulation and execution for the Morales hypervisor. The workflow verifies core logic (including 84 privileged registers), automates boilerplate instruction proofs, and found 21 bugs—from a physical lock‑bit leakage that breaks isolation to a compressed‑load immediate off‑by‑one and MEPC alignment issues—trading full end‑to‑end mechanization for practical, fast developer feedback.

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" chapters (8)

1. 0:00Introduction
2. 0:44Motivation for verification
3. 5:21Classic correctness concepts
4. 10:16Faithful emulation explained
5. 13:49Case study: Morales hypervisor
6. 21:59Bugs discovered through lightweight verification
7. 24:04Impact and future of specs
8. 25:09Q&A

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