Optimizing the Annoying Stuff: Reducing Costs Obscured by the Abstract Circuit Model
summary
Shows that routing and compilation choices—and where Clifford corrections live—change costs far more than gate counts: T/magic-state factories shrink 10–100×, deferred-Clifford layouts prove hundreds× less efficient, and a lattice-surgery ripple-carry redesign yields nearly 4× smaller adder blocks. Uses lattice surgery, ZX calculus and a visual editor (Crumble) to attach corrections to magic states for reaction-limited computation, produces a tiled, working adder layout with modest slack to avoid a self-intersection bug.
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chapters (18)
- 0:00Quantum Industry Day intro
- 2:36Annual overview
- 6:16Optimizing costs via implementation
- 7:39Classical adders and hardware
- 9:46Quantum adders and fault tolerance
- 10:49Surface code computations
- 12:57Clock speed and decoder latency
- 13:59ZX calculus for fault tolerance
- 14:42Lattice surgery operations
- 16:34Execution strategies for adders
- 17:41T state prep evolution 2018-2024
- 18:44Optimizing adders with identity
- 20:58Layout and routing optimizations
- 22:49Translating to quantum circuits
- 23:52Common adder mistakes
- 24:38Key takeaways
- 25:42Ignored error correction details
- 28:42Q&A with Craig Gidney
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