Analyzing cacheline contention using perf c2c
summary
Demonstrates using perf c2c to locate true cacheline contention in Postgres and traces how that led to snapshot scalability work in PG 14. Covers cache hierarchy, coherence protocol behavior, and how HitM events reveal modified-line transfers across cores/sockets. Shows a concrete case: buffer descriptor false sharing around lock/state fields, and a five-line padding change (separating lock from read-mostly fields) raises pgbench throughput from ~7,500 to ~10,000 tx/s at 16 clients. Describes recording and reporting tips and using buffer descriptor padding as a practical fix.
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chapters (10)
- 0:00Introduction to cacheline contention
- 1:13Hardware cache structure basics
- 8:46What is cacheline contention
- 13:20False sharing scenarios explained
- 16:51Solutions to cacheline issues
- 18:57What is perf c2c
- 23:37Analyzing with perf c2c report
- 34:09Case study: buffer descriptor fix
- 40:11Caveats and performance impact
- 41:59Q&A session
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