Special Session I
summary
Seven simulators are released on GitHub to run parallel simulation of chiplet systems with accurate interposer models and claims of scaling to millions of cores; an all‑digital 2.5D PHY is implemented in standard cells, EM‑extracted and simulated at 6.4–6.5 Gbps per lane and ~0.41 pJ/bit; a MTR composability method enforces boundary turn restrictions to guarantee deadlock‑freedom without global CDG; iterative chiplet+package co‑design raises core frequency from ~245 MHz to ~300 MHz; multi‑objective GA finds Pareto hardware/mapping tradeoffs.
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