The foundation of C++20 atomics
summary
Explains what C++20 atomics actually guarantee by mapping them to real hardware: x86 TSO behavior, why stores sit in a store queue and why loads may see younger stores via store-to-load forwarding, when fences become necessary, and how out-of-order execution and register renaming create the 100-cycle store-address vs 2-cycle load problem. Presents concrete microarchitecture mechanisms, examples with cycle counts, and which compiler/hardware cooperation is required for correct and efficient atomic code.
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chapters (18)
- 0:00Introduction to atomics
- 2:55Tightly coupled processors
- 4:33Consistency vs coherence
- 5:32Memory ordering issues
- 7:18The critical section problem
- 9:37Causes of inconsistency
- 13:35Sequential consistency
- 15:10Total store ordering
- 20:47TSO vs sequential consistency
- 23:16Why hardware uses buffers
- 26:01Data dependencies
- 29:37Out-of-order execution
- 34:19Data flow machines
- 38:52Memory ambiguity
- 42:30Load scheduling challenges
- 47:07Store-load forwarding
- 51:01Content addressable memory
- 53:45Store buffer mechanics
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