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Industry panel: Memory management priorities for the next few years

Panelat ISMM 2022 · on Tuesday, 2022-06-14
slides:none on file

Claims: garbage-collected runtimes face hundreds-of-gigabyte heaps so non-compacting mark‑and‑sweep hits scalability limits while Julia moves toward mostly compacting parallel GC with aging generations; allocators show that a huge-page‑aware backend called Temeraire and per‑CPU caches improve TLB locality and overall app performance; memory‑safe architectures like CHERI use a page map of metadata and enable a practical memory coloring scheme (4‑bit color, 16 colors) that makes revocation ~16× rarer with an earlier one‑bit prototype costing ~10 cycles. Benchmarks combine SPEC, microtests, and 1% fleet rollouts.

AI-written summary · about

  1. 0:00Start
  2. 10:27Introduction
  3. 18:20Improve Application Performance
  4. 19:30Memory Safe Architecture
  5. 26:32Memory Coloring
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