How understanding RAM sped up a 4G/5G packet gateway by 30%
summary
Examines how detailed knowledge of RAM behavior reduced latency and raised throughput by about 30% in a 4G/5G packet gateway. Describes the memory-access bottleneck (cache vs RAM latency), profiling of memory patterns, and engineering techniques—cache-friendly data layouts, prefetching, batching, and reduced memory copy—to cut expensive DRAM stalls in a high-throughput networking dataplane.
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chapters (14)
- 0:00Introduction
- 1:09What is UPF in networks
- 5:26Choosing DPDK over Linux
- 6:52Performance problem
- 8:16What are TLB and DTLB
- 11:12TLB overflow problem
- 13:01Using huge pages
- 15:13L3 cache latency issue
- 16:38Packet processing pipeline
- 18:05Data structure optimization
- 21:43Reducing structure size
- 23:50Optimization results
- 26:22Conclusions and application
- 26:45Q&A
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