An Empirical Guide to the Behavior and Use of Scalable Persistent Memory

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Large-scale experiments (10,000 microbenchmarks, ~300 machine-hours on Intel-supplied 2-socket hardware with 3 TB Optane made from 256 GB DIMMs) show Optane NVDIMMs use a 256-byte device block and an on-device merge buffer, produce 2–3x DRAM latency for reads (writes acknowledged early), and exhibit odd bandwidth behavior: peak at 512 B, a valley at 4 KB caused by IMC/interleave contention, and write bandwidth that saturates around five threads. Practical rules: avoid small random accesses, use non-temporal stores, limit threads per DIMM, and avoid mixed NUMA accesses.

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" chapters (17)

1. 0:00Intro
2. 1:16Outline
3. 2:20Background: Optane in the Machine
4. 4:21Background: Optane Internals
5. 6:29Background: Optane Interleaving
6. 7:25Basics: Our Approach
7. 8:38Test Platform
8. 9:13Basics: Latency
9. 10:10Basics: Bandwidth
10. 12:54Avoid small random accesses
11. 13:36Lessons: Optane Buffer Size
12. 14:23Use ntstores for large writes
13. 16:47Lessons: Contention at Optane Buffer
14. 17:47Lesson: Contention at IMC
15. 20:18Limit threads accessing one NVDIMM
16. 20:32Avoid mixed and multi-threaded NUMA accesses
17. 21:19Conclusion