“Improving Performance Through Compiler Switches..."
summary
Benchmarks compare GCC 6.2, Clang 3.9 and Intel 17 on streaming, reductions and a template-heavy SIMD test (and HPCG). Results show compiler flags and architecture matter: GCC emits scalar code at O2 that is ~3x slower on Skylake unless O3+arch is used; binary text size jumps ~91% O0→O2 for GCC (Clang ~41%, Intel much larger); manually using AVX FMA and non-temporal stores yields a 30% speedup that compilers often miss; fast-math effects vary and must be validated per workload.
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chapters (22)
- 0:00Introduction to Compiler Flags
- 0:55Scientific Computing Context
- 2:36HPC Challenges and Power Issues
- 4:24Multicore Trends and Software
- 6:29Understanding Compiler Switches
- 8:42Optimization Categorization
- 10:44The Myths of Optimization
- 12:27Floating Point Arithmetic
- 14:29Reduction Operation Analysis
- 17:07Code Bloat and Runtime
- 21:22Under the Hood of Optimizers
- 24:05Fast Math and Unsafe Ops
- 27:57Architecture and Loop Flags
- 31:46SAXPY Benchmark Introduction
- 34:55SIMD Instructions Refresher
- 37:28SAXPY Performance Results
- 41:57Assembly Analysis
- 43:44Clang and Intel Performance
- 50:10Relative Performance Analysis
- 52:35Intrinsics and Non-Temporal
- 55:54Conclusion and Benchmarking
- 59:40Q&A and Best Practices
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