Unlock the Power of Parallel Computing With SWAR (SIMD Within A Register)
summary
Claims that SIMD-like speed is possible using ordinary CPU registers by packing lanes and using bitwise tricks to prevent lane‑crossing, so no special SIMD hardware required. Delivers a header-only "zoo" library with equality, safe/unsafe arithmetic, and an optimized strlen that uses aligned speculative loads and a find-first-empty shortcut. Benchmarks show the portable zoo version scans a corpus in ~5,500 ns vs ~5,000 ns for one NEON baseline, and combining SWAR with NEON yields ~70% of hand‑tuned assembler performance, so the approach is practical and competitive.
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chapters (9)
- 0:00SWAR introduction and benefits
- 6:51Lane overflow in SWAR
- 11:54Equality checks with SWAR
- 19:03Boolean SWAR concepts
- 21:12Generalizing SWAR
- 27:17String length with SWAR
- 36:16Scaling SWAR widths
- 40:29Zoo library basics
- 42:56Q&A
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