Noise-Aware Calibration-Based Adaptive Gate Folding for Linear Zero-Noise Extrapolation
summary
Proposes a noise-adaptive mapping plus calibration-guided selective folding that uses device calibration to build an error-rate accumulation matrix, then folds gates nonuniformly before applying linear zero-noise extrapolation. Implements selective gate folding on superconducting hardware and a noisy simulator, tests on circuits up to 18 qubits (sim) and a 14-qubit BV, and reports fidelity gains of about 22% on simulator and 26% on real IBMQ hardware, with mitigation degrading beyond ~6–7 qubits.
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chapters (10)
- 0:00Noise-aware calibration-based adaptive gate folding
- 1:27Zero-noise extrapolation fundamentals
- 4:21Limitations of unitary folding
- 6:29Noise-adaptive mapping and error rates
- 7:55Calibration-guided selective folding
- 8:58Experimental setup and circuits
- 10:02Results on simulator and hardware
- 12:33Conclusion and future research
- 14:18Q&A: Architecture generalization
- 15:25Q&A: Real device performance
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